The present invention relates to the fabrication of semiconductor devices. In particular, the present invention relates to the fabrication of flash memory semiconductor devices. With still greater particularity, the present invention relates to testing procedures, used during semiconductor device fabrication, for determining the width of the active region disposed between shallow trench isolation structures which isolate circuit elements in flash memory arrays.
Flash memory devices are used in wide array of electronic devices, such as computers, digital cameras, and personal digital assistants. In all such applications, increasing memory capacity and reducing electrical consumption are desirable. The primary related art method for increasing capacity and decreasing power requirements has been to make each succeeding generation of devices smaller. The current technology involves geometries of less than 0.25-xcexcm. As the circuit elements become smaller, problems arise relating to interference between different elements.
The former generation of flash memory used local oxidation of silicon (LOCOS) technology to isolate circuit elements. LOCOS has been replaced in the current generation by shallow trench isolation (STI) technology to isolate circuit elements. In STI technology, STI structures are typically formed between circuit elements which are commonly referred to as metal oxide semiconductor field effect transistors (MOSFETs). MOSFETs include a source region and a drain region of doped semiconductor material, between which current traverses. This current is controlled by a gate which is insulated from the source and drain regions by a thin layer of insulating material, such as a tunnel oxide. As is conventional, multiple gate layers are insulated from each other by insulating layers. A xe2x80x9cfloatingxe2x80x9d gate is produced which controls the signal and functions according to the principle of quantum tunneling. In STI technology, the source, drain, and floating gate are formed between the shallow trench isolation structures formed by etching into the substrate of semiconductor materials, such as silicon, germanium, or gallium arsenide, thereby forming trenches, and, thereafter, by filling the trenches with an insulating material. A thin layer of an insulating material, such as silicon oxide or silicon dioxide (e.g., SiO, SiO2, respectively), is formed over the active region between trenches, the insulating material to later form a tunnel oxide layer. The floating gate is formed from a semiconducting material (e.g., a polycrystalline silicon) on this insulating material. In operation, a small charge on this floating gate can control the current flow between the source region and the drain region. The active region width, sometimes also referred to as xe2x80x9creal overlapxe2x80x9d width, is the distance between two shallow trench isolation structures.
A problem has arisen in STI technology where opposing end portions of a tunnel oxide layer, which are respectively disposed adjacent the opposing upper corners of the shallow trench isolation structures, are being thinned. This thinning of the opposing end portions is difficult to measure and to quantify. While the presence of thinning opposing end portions may be made by monitoring the Fowler-Nordheim (F-N) tunneling current, such a measurement, in and of itself, is merely qualitative and provides no measure of, nor any other information regarding, the active region comprising a floating gate and source/drain regions.
This active region width, affected by the thinning opposing end portions, has a large and notable impact on the programming current distribution and the core gain. Thus, a need exists for a method of accurately determining the width of the active region between shallow trench isolation structures for fabricating a flash memory semiconductor device and a device thereby formed.
Accordingly, the present invention provides a solution to the foregoing related art problems in a method for accurately determining the width of the active region between shallow trench isolation structures by using a noninvasive nondestructive testing procedure for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present device comprises at least one composite capacitor structure having a plurality of capacitor elements (e.g., a MOS capacitor element). The present method measures the respective gate current of each at least one composite capacitor structure from the gate through the tunnel oxide layer to the active region, where each at least one composite capacitor structure has an identical active region length (i.e., equal source/drain lengths) but also has a distinct active region width and a distinct predetermined width. The respective gate current value of each at least one composite capacitor structure facilitates determining the active region widths for various MOS capacitor elements by using the noninvasive nondestructive testing techniques. Since the respective measured gate current values correspond to the various active regions where tunnel oxide thinning occurs, the corresponding active region widths can be determined.
The present method involves measuring the gate current (e.g., a Fowler-Nordheim tunneling current) flowing from a floating gate through a tunnel oxide layer to an active region. Since the Fowler-Nordheim tunneling current is proportional to the total area of the composite capacitor structure, where the oxide electric filed is the same, the total current is proportional to the active region width at the STI structure has been formed. The active region width is then mathematically derived from the gate current values and the predetermined width as the tunneling current value is proportional to the active region width.
The present method provides crucial information for fabricating a flash memory semiconductor device, because the channel width, corresponding to the active region width, affects the following parameters: the programming current, the programmed voltage threshold, the threshold voltage distribution, as well as the core gain. These parameters, in combination, substantially influence the construction of a flash memory semiconductor devices and their associated technology.